Job Description

ph3Description /h3 /brpA cover letter outlining your motivation to move to Oslo, Norway is required with submittal of your CV. /p /brpWe design and verify: timing and control signals for CMOS pixel array readout analog/digital converters; image signal processing (ISP) functions such as black level compensation (BLC), defect pixel correction (DPC), lens correction, and high dynamic range processing; serial and parallel I/O interfaces (e.g. I2C, MIPI) for use in OMNIVISIONS’s Image Sensors. As the designs are targeted for the automotive market, there is also focus on design for safety. The team handles all tasks of the chip development cycle including product specification, architecture definition, RTL design, verification, synthesis, DFT, STA, gate-level-simulation, power analysis optimization, FPGA emulation, chip bring-up, validation debug. /p /brpAs a Digital Design Engineer you will be working on the design and development of advanced CMOS Image Sensors (CIS). We are looking for someone with strong digital design expertise who is able to handle various aspects of the design flow from specification to tape-out. In this role you’ll have the opportunity to grow into a technical project leader taking on more responsibility. This position calls for someone who is highly motivated, self-driven, a team player and willing to learn. /p /brh3Responsibilities /h3 /brul /brliDesign and verification of digital IP for CIS /li /brliDefine chip level architecture taking into consideration power, performance area trade-offs; build module specification /li /brliPerform logic synthesis, work with backend team for floor planning, STA and DFT /li /brliParticipate in project planning and progress tracking /li /brliFull-chip integration and verification /li /brliSilicon bring-up, validation and debug /li /br /ul /brh3Qualifications /h3 /brul /brliMinimum MSEE with 1-2 yrs OR BSEE with 3-4 years of digital design experience /li /brliExpertise in ASIC design flow: RTL coding, simulation, logic synthesis, STA DFT. /li /brliKnowledge of all aspects of chip development cycle from design specification, architecture definition, low-power design, tape-out, chip validation and debug /li /brliKnowledge of assertion-based formal verification is a plus /li /brliKnowledge of ASIL is a plus /li /brliImage processing/DSP knowledge is a plus /li /brliExcellent command of English as a working language /li /brliAbility to work collaboratively with people across multiple functional areas /li /br /ul /p #J-18808-Ljbffr